Thin film transistor liquid crystal display (TFT-LCD) mainly includes a color filter (CF) substrate, an array substrate and liquid crystals filled between the two substrates. A sealant is applied at peripheries of the two substrates so as to adhere them together and seal up the liquid crystals therebetween. Usually, the array substrate is of an area slightly greater than the color filter substrate, and corresponding room is left at its additional portion mainly for the bonding of a gate driving unit such as a gate integrated circuit (IC) and a source driving unit such as a source IC.
Referring to FIGS. 1-3, FIG. 1 is a schematic view of an existing array substrate, FIG. 2 is an enlarged view of a corner of the array substrate in FIG. 1, and FIG. 3 is a sectional view taken along a plane A-A′ in FIG. 2.
As shown in FIG. 1, an array substrate 100 includes a display region 101 and a non-display region 102 arranged at a periphery of the display region. The non-display region 102 includes a sealant region 1021 arranged at a periphery of the display region 101 and a peripheral region 1022 arranged at a periphery of the sealant region 1021. A peripheral layout gate (PLG) line 202 is arranged at the peripheral region 1022. The PLG line 202 is a line for transmitting a voltage and a control signal desired for a gate electrode from a source driving unit such as a source IC to a gate driving unit such as a gate IC, so as to ensure a normal operation of the gate IC. In FIGS. 2-3, 201 represents a base substrate, 202 represents the PLG line, 203 represents a passivation layer, 204 represents a PLG connection line, and 205 represents a via-hole in the passivation layer 203. As shown in FIG. 3, the PLG connection line 204 is connected to the PLG line 202 through the via-hole 205 in the passivation layer 203, so that the PLG line 202 is connected to the driving unit (the gate driving unit or the source driving unit). As shown in FIG. 1, an existing PLG line 202 is arranged at an edge of the array substrate and easily damaged due to such factors as external force, scratch or corrosion. As a result, it is impossible for the gate driving unit to receive the desired voltage and signal, and abnormal display will occur.